1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and more particularly, to a semiconductor device comprising a field effect transistor including a strip shaped fin, and its manufacturing method.
2. Description of the Related Art
Conspicuously high performance of an integrated circuit has recently been achieved by miniaturization of elements which constitute a semiconductor device. Such miniaturization has been achieved by reducing of a gate length and/or thinning of a gate insulator of a metal insulator semiconductor field effect transistor (MISFET) used in a semiconductor device, e.g., a logical circuit, or a storage device, based on a so-called scaling law.
In the MISFET whose gate length is, e.g., 30 nm or less, it is a significant challenge to suppress short channel effects. As one of the suppressing methods, for example, Jpn. Pat. Appln. KOKAI Publication No. 2003-298051 discloses a Fin-FET in which a projected region is formed by finely processing a silicon substrate into a strip shape (referred to as a fin, hereinafter), and an MISFET of a 3-dimensional structure is formed therein. This example is a double gate Fin-FET in which a reverse U-shaped gate electrode is formed on one fin. In the double gate Fin-FET, equal potential is applied to the gate electrode covered on both sides of the fin, and channels are formed in side faces of the fin from both sides. In a fully depleted Fin-FET in which a depletion layer extended from the channel spreads over the entire thickness of the fin, when polysilicon is used for the gate electrode as typically used thereto, there is a difficulty in controlling a threshold voltage of the Fin-FET to a desired value. This problem is related to a work function of a gate electrode material, and can be controlled by using a material, which has a work function near a middle of an energy gap of silicon (mid-gap). However, it is difficult to find a proper material which has such characteristics.
Thus, a back gate Fin-FET has been proposed as a semiconductor device that realizes a desired threshold voltage by controlling a potential of a channel region (see, e.g., Y. K. Liu, M. Masahara, K. Ishii, T, Tsutsumi, T. Sekigawa, H. Takashima, H. Yamauchi and E. Suzuki: “Flexible Threshold Voltage Fin-FETs with Independent Double Gates and an Ideal Rectangular Cross-Section Si-Fin-channel”, IEDM Tech. Dig., pp. 986-988, 2003). The back gate Fin-FET comprises a set of gate electrodes disposed to face side faces of the fin and to be independent of each other, i.e., a front gate and a back gate. Different potentials can be applied to the front gate and the back gate. For example, the front gate is used to control a channel formed in one side face of the fin, and the back gate is used to control a potential of the channel region. It has been reported that such a back gate Fin-FET can control a threshold voltage well.
Each of the two types of Fin-FET is in a single fin structure in which two gate electrodes are formed to one fin. Consequently, a channel width is narrow, i.e., a fin height is low, which is unsuitable to a semiconductor device for driving a large current. Since it is not easy to increase an effective channel width by setting a fin height to be high enough, a multi Fin-FET that comprises a plurality of fins arranged close to and in parallel one another has been presented in, e.g., “Sub-20 nm CMOS Fin-FET Technologies”, IEDM Tech. Dig., pp. 421-424, 2001 by Yang-Kyu Choi, Nick Lindert, Peiqi Xuan, Stephen Tang, Daewon Ha, Erick Anderson, Tsu-Jae King, Jeffrey Bokor, and Chenming Hu. A structure described therein is a double gate multi Fin-FET, and there is no description of a back gate multi Fin-FET. In the double gate multi Fin-FET, one thin long gate electrode is vertically formed across the fins and one predetermined potential is applied to the gate electrode.
However, to realize the back gate multi Fin-FET, different potentials must be applied to two independent gate electrodes. Additionally, in the Fin-FET, since a source/drain and a channel are formed in a very narrow fin, reductions in parasitic resistance and parasitic capacitance are significant challenges to increase a current driving force and to achieve a high-speed switching operation. Yang-Kyu Choi et. al., have presented in the aforementioned paper a method of selectively growing a germanium layer in the source/drain of the fin to reduce parasitic resistance. However, a problem of an increase in the number of process steps is inherent in this method.
Therefore, there is a need to provide a semiconductor device comprising a multi Fin-FET structure capable of suppressing the short channel effects, controlling the threshold voltage, driving a high current, and operating in a high-speed, and its manufacturing method.